Among the several design-for-testability (DFT)methods which have been proposed to simplify the task of sequential test pattern generation, the partial scan method has become increasingly popular. Unlike full scan where all the flip-flops (FFs) in a circuit are made observable and controllable, the partial scan method selects a subset of FFs for scan. While it may be possible to achieve test efficiency comparable to that achieved by a full-scan circuit, a partial scan circuit usually requires less chip area and delay overheads, and shorter test application times due to the presence of fewer FFs in the scan chain.
However, the scan-based methods have a disadvantage that the test application time is very large compared to non-scan designs because the test vectors in the scan-based methods have to be shifted through the scan chain. Reduction of test application time has been addressed in several ways, e.g. arranging scan flip-flops in parallel scan chains and reconfiguring scan chains. In the parallel scan chain approach, the number of parallel scan chains, and hence the number of vectors that can be shifted in parallel, is limited by the minimum of the number of primary inputs and primary outputs of the circuit. The reconfigurable scan chain approach is limited by the ability of the circuit to be decomposed into a set of kernels, which are disjoint portions of logic that can be tested independently. Controllability and observability points arc also provided in silicon-based solutions such as CrossCheck described in the article by T. Gheewala entitled "CrossCheck: A Cell Based VLSI Testability Solution" in Proc. DAC, pages 706 to 709, 1989 and in the article by S. J. Chandra et all entitled "ATPG Based on a Novel Grid-Addressable Latch Element" in Proc. DAC, pages 282 to 286, 1991. Test application is slow as a result of the need to scan observation and control points and the transmission delays along long diffusion lines used to select the observation and control points. On the other hand, non-scan DFT techniques do not require scanning of any FFs, thus eliminating the need to shift test vectors through scan chains and hence, greatly reducing the test application time.
However, the major disadvantage of scan-based DFT techniques is that the test vectors cannot be applied to the circuit at the operational speed of the circuit. That is, test vectors cannot be applied at consecutive clock cycles. The inability of scan designs to be tested "at-speed" assume significance in view of recent studies, which show that a stuck-at test set applied at-speed identifies more defective chips than a test set having the same fault coverage but applied at a lower speed. As a result of these studies, researchers began to investigate non-scan DFT techniques to make sequential circuits testable by introducing controllability and observability points. The leasability of non-scan DFT techniques to produce testable sequential circuits with high test efficiency was demonstrated in an article by V. Chickermane et al, entitled "Non-Scan Design-for-Testability Techniques for Sequential Circuits" in Proc. Design Automation Conf., pages 236 to 241, June 1993. The main advantage of the non-scan designs is that the test vectors can be applied at-speed.
Recently, several high level synthesis approaches have been proposed to generate easily testable data paths for both Built-In-Self-Test (BIST)-based testing methodology, and Automatic Test Pattern Generation (ATPG) methods. Test statement insertion has been used in the behavioral specification to improve testability of the circuit. An approach to generate testable data paths, by minimizing the number of self-loops, is known. Several techniques have been suggested to synthesize data paths without loops, by using proper scheduling and assignment, and scan registers to break loops.
Almost all BIST-based methods assume a scan design methodology since random testing is not well-suited for sequential circuits. Also, almost all the ATPG-based high level synthesis for testability approaches, with the exception of methods proposed in an article by T. C. Lee et al entitled "Behavior Synthesis for Easy Testability in Data Path Allocation" in the Proceedings of the Int'l Conf. on Computer Design 1992 and T. C. Lee et al, "Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan add Partial Scan Environments" in the Proceedings of Design Automation Conference, pages 292 to 297, 1993 assume the rise of scan registers to make the data paths testable. However, the non-scan techniques presented in the Lee et al articles produce testable data paths only when the circuit designs have a large number of primary inputs (PIs) and primary outputs (POs), and do not have any loops. For instance, for the design example of a 5th order Elliptical Wave Filter, the Lee et al non-scan scheme could not make the data path testable. In general, most circuit designs have a small number of primary inputs and primary outputs. In addition, most circuits have several types of loops formed, partly due to the presence of such loops in the specification itself and partly due to resource sharing employed to generate area-efficient data paths. Consequently, the existing high-level testability techniques either are based on using scan methods or are not suitable for practical data paths having loops.
Several techniques have been developed to improve the testability of circuits by exploiting the RT-level (register transfer-level) description of designs. Transformation and optimization techniques were proposed in an article by S. Bhattacharya et al entitled "Transformations and Resynthesis for Testability of RT-Level Control-Data Path Specifications", in IEEE Trans. on VLSI Systems, 1 (3), pages 304 to 318, Sept. 1993 which utilize RT-level information to generate optimized designs that are 100% testable under full scan. Chickermane, Lee, and Patel in two articles entitled "Design for Testability Using Architectural Descriptions" in Proc. of the Intl Test conf. pages 752 to 761, Nov. 1992 and entitled "A Comparative Study of Design for Testability Methods Using High-Level and Gate-Level Descriptions" in Proc. of the Intl Conf on Computer-Aided Design, pages 620 to 624, Nov. 1992, showed that the use of RT-level information to select scan flip-flops results in significantly better performance when compared to techniques limited to gate-level information only. Steensma, Catthoor, and De Man in an article entitled "Partial Scan at the Register-Transfer Level" in Proc. ITC pages 488 to 497, Oct, 1993, proposed an efficient partial scan methodology applicable to data paths described at the RT-level. The method is based on eliminating loops by making existing registers scannable, or by adding extra transparent scan registers. In an article by H. Harmanani et al entitled "An improved Method for RTL Synthesis with Testability Tradeoffs" in Proc. of the Intl Conf on Computer-Aided Design, pages 30 to 35, Nov. 1993, an RT-level method was presented to generate vvself-testable RTL data paths, using allocation and automatic test point selection to reduce the sequential depth from controllable to observable registers. Like the high-level synthesis for testability techniques summarized above, all the existing RT-level techniques are scan-based, and cannot generate testable data paths without the use of scan.
It is known that the dependencies of the flip flops (FFs) of a sequential circuit may be captured by an S-graph. It has been empirically determined that sequential test generation complexity may grow exponentially with the length of the cycles in the S-graph. An effective partial scan approach selects scan flip flops in the minimum feedback vertex set (MFVS) of the S-graph, so that all loops, except self-loops, are broken, and the sequential depth is minimal. Existing non-scan techniques also restrict themselves to flip flops as the nodes to be made controllable. The non-scan technique presented in Chickermane et al supra selects flip flops to load from primary inputs (add control point) such that the loops in the circuit are broken.
Breaking all the cycles in a circuit by scan flip flops may be very expensive in terms of the scan overhead, especially for data paths which have a tendency to have complex loop structures. Also, the presence of a large number of flip flops in the scan chain increases the test application time. For non-scan designs, effective controllability of flip flops is limited by the number of primary inputs available.